1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More specifically, the invention is in the field of fabrication of bipolar transistors.
2. Related Art
As Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) technology continues to advance in an effort to achieve increased device speed and reduced power consumption, it becomes more difficult to transparently integrate high performance bipolar devices, such as high performance NPN devices, with CMOS devices. High performance NPN devices, such as NPN silicon-germanium (SiGe) heterojunction bipolar transistors (HBT), require a shallow emitter-base junction and low emitter resistance while CMOS devices require a CMOS process with a low thermal budget for advanced BiCMOS technology.
By way of background, in a BiCMOS process, rapid thermal processing (RTP), which is a high temperature, fast annealing process, is typically used to activate dopants and repair implant damage in the bipolar and CMOS regions of the semiconductor die. Typically, arsenic is used as an emitter dopant for NPN devices because arsenic has a high solid solubility limit, which allows the emitter to be heavily doped with arsenic to achieve a low emitter resistance. Arsenic also has a low diffusion coefficient, which limits the diffusion of arsenic into the base during the RTP process to achieve a shallow emitter-base junction.
As bipolar and CMOS devices are scaled down in advanced BiCMOS processes, CMOS device formation requires a reduced thermal budget. However, the reduced thermal budget results in lower activation of arsenic and, consequently, increased emitter resistance, which reduces NPN device performance. An N type dopant with a lower activation temperature, such as phosphorus, could be used in place of arsenic to dope the emitter of the NPN device. However, the high diffusion coefficient of phosphorus causes phosphorus to diffuse significantly into the base region of the NPN device during RTP. As a result, phosphorus causes an undesirably deep emitter-base junction to be formed in the NPN device, which reduces performance of the NPN device.
Thus, there is a need in the art for an NPN device having low emitter resistance and a shallow emitter-base junction that can be effectively integrated with a CMOS device in a BiCMOS process.